Design of CIC based decimation filter structure using FPGA for WiMAX applications

This paper focuses on the efficient design and FPGA realization of CIC based decimation filter structure for WiMAX application. This structure reduces the sampling rate at each section and lower the power consumption in each section with improved magnitude response. The magnitude responses and device utilization of the filter with different combinations considering different stages are estimated and compared with the existing structures. MATLAB Simulink environment is used for design and Xilinx Virtex-V XC5VLX110T-3ff1136 FPGA is utilized for implementation. It is observed from the results that the passband droop and stopband characteristics of this filter structure are improved when the decimation factor of first section is less compared to second section (M1 < M2). On the other hand power consumption of the filter is less when the decimation factor of first section is high compared with second section (M1 > M2). The results show that the passband droop improvement is about 38% and stopband attenuation improvement is of 33% for the decimation factor M = 8.