High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory

This work proposes a novel p-type boron-doped floating gate for n-channel split-gate flash memory. A lower program voltage, with a programming time of 7 mu s, results in five times of the conventional source-side injection programming efficiency, a 5% wider program/erase window, and more reliable endurance characteristics. Additionally, a 2 Mbit embedded flash Intellectual Property (IP) has been successfully implemented and statistically compared. The lower program voltage reduces concerns around the high-voltage decoder, the charge pump efficiency, and the array efficiency beyond 90 nm nodes. The new p-doped split-gate structure provides a very promising solution for advanced embedded split-gate flash memory beyond the 90 nm node.