Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors

被引：20

作者：

Han, SW

Yoon, E

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, Taejon 305701, South Korea

[2] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA

来源：

ELECTRONICS LETTERS | 2006年 / 42卷 / 06期

关键词：

D O I：

10.1049/el:20064189

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An area-efficient correlated double sampling (CDS) circuit is proposed. In conventional designs, most of the area of CDS circuits is occupied by two large on-chip sampling capacitors. A new CDS scheme is devised using only one sampling capacitor. The proposed CDS circuit has been successfully realised in a small two column pitch of 7.2 mu m in a test chip fabricated using 0.18 mu m CMOS process and has demonstrated fixed pattern noise less than 0.46%.

引用

页码：335 / 337

页数：3

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