Low-power, wide-range time-to-digital converter for all digital phase-locked loops

被引：7

作者：

Jeong, C. -H. ^{[1
]}

Kwon, C. -K. ^{[1
]}

Kim, H. ^{[2
]}

Hwang, I. -C. ^{[3
]}

Kim, S. -W. ^{[2
]}

机构：

[1] Korea Univ, Dept Nano Semicond Engn, Seoul, South Korea

[2] Korea Univ, Dept Elect Engn, Seoul, South Korea

[3] Kangwon Natl Univ, Dept Elect & Elect Engn, Chunchon, South Korea

来源：

ELECTRONICS LETTERS | 2013年 / 49卷 / 02期

关键词：

D O I：

10.1049/el.2012.3434

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A time-to-digital converter (TDC) for a low-power, wide-range all digital phase-locked loop (ADPLL) is presented. The proposed TDC uses an enabling signal with variable duration to achieve low power and wide range. For verification purpose, the ADPLL is fabricated in a 0.11 mu m CMOS technology. The ADPLL dissipates 6.02mW at an output frequency of 1.68GHz and its output frequency is measured as 0.24-1.68 GHz from a 1.2 V supply.

引用

页码：96 / 97

页数：2

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