DESIGN AND IMPLEMENTATION OF A MULTI-MODE HARRIS CORNER DETECTOR ARCHITECTURE

In this paper, we present a configurable architecture for corner detection in images based on the well-known Harris corner detection algorithm, and we demonstrate a field programmable gate array (FPGA) implementation of the proposed architecture. Our architecture is designed to be configurable across diverse operational trade-offs, which makes it useful for integration into a wide variety of application scenarios. We apply lightweight dataflow methods for design and implementation of our configurable architecture, and for experimentation with alternative combinations of transformations for design optimization across throughput, latency, and FPGA resource requirements. By using different levels of resource-sharing - in particular resource sharing within and across individual dataflow graph modules - we are able to systematically arrive at a set of efficient architectural configurations using a unified, model-based methodology.