Aurora: A Thermally Resilient Photonic Network-on-Chip Architecture

被引:0
|
作者
Qouneh, Amer [1 ]
Li, Zhongqi [1 ]
Joshi, Madhura
Zhang, Wangyuan
Fu, Xin
Li, Tao
机构
[1] Univ Florida, Gainesville, FL 32605 USA
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
With silicon optical technology moving towards maturity, the use of photonic network-on-chip (NoCs) for global chip communication is emerging as a promising solution to communication requirements of future many core processors. It is expected that photonic NoCs will play an important role in alleviating current power, latency, and bandwidth constraints. However, photonic NoCs are sensitive to ambient temperature variations because their basic constituents, ring resonators, are themselves sensitive to those variations. Since ring resonators are basic building blocks for photonic modulators, switches, multiplexers, and demultiplexers, variations of on-chip temperature pose serious challenges to the proper operation of photonic NoCs. Proposed methods that mitigate the effects of temperature at device level are either difficult to use in CMOS processes or not suitable for large scale implementation. In this paper, we propose Aurora, a thermally resilient photonic NoC architecture design that supports reliable and low bit error rate (BER) on-chip communications in the presence of large temperature variations. Our proposed architecture leverages solutions at both device and architecture layers that synergistically provide significant improvements. To compensate for small temperature variations, our design varies the bias current through ring resonators. For larger temperature variations, we propose architecture-level techniques to re-route messages away from hot regions, and through cooler regions, to their destinations, thereby lowering BER. Our simulation results show that Aurora provides a robust architectural solution to handle temperature variation effects on future photonic NoCs. For instance, average BER and message error rate (MER) are reduced by 78% and 30% respectively when the combined device and architectural technique (SPF) is applied. From the perspective of power efficiency, Aurora is also superior to conventional photonic NoC architectures by as much as 33%.
引用
收藏
页码:379 / 386
页数:8
相关论文
共 50 条
  • [21] Hierarchical Architecture for Network-on-Chip Platform
    Lin, Liang-Yu
    Lin, Huang-Kai
    Wang, Cheng-Yeh
    Van, Lan-Da
    Jou, Jing-Yang
    [J]. 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2009, : 343 - +
  • [22] Silicon photonic network-on-chip and enabling components
    Hu Ting
    Qiu Chen
    Yu Ping
    Yang LongZhi
    Wang WanJun
    Jiang XiaoQing
    Yang Mei
    Zhang Lei
    Yang JianYi
    [J]. SCIENCE CHINA-TECHNOLOGICAL SCIENCES, 2013, 56 (03) : 543 - 553
  • [23] Silicon photonic network-on-chip and enabling components
    Ting Hu
    Chen Qiu
    Ping Yu
    LongZhi Yang
    WanJun Wang
    XiaoQing Jiang
    Mei Yang
    Lei Zhang
    JianYi Yang
    [J]. Science China Technological Sciences, 2013, 56 : 543 - 553
  • [24] SecONet: A Security Framework for a Photonic Network-on-Chip
    Bashir, Janibul
    Goodchild, Chandran
    Sarangi, Smruti Ranjan
    [J]. 2020 14TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2020,
  • [25] Silicon photonic network-on-chip and enabling components
    HU Ting
    QIU Chen
    YU Ping
    YANG LongZhi
    WANG WanJun
    JIANG XiaoQing
    YANG Mei
    ZHANG Lei
    YANG JianYi
    [J]. Science China Technological Sciences, 2013, (03) : 543 - 553
  • [26] Silicon photonic network-on-chip and enabling components
    HU Ting
    QIU Chen
    YU Ping
    YANG LongZhi
    WANG WanJun
    JIANG XiaoQing
    YANG Mei
    ZHANG Lei
    YANG JianYi
    [J]. Science China(Technological Sciences)., 2013, 56 (03) - 553
  • [27] Software-Defined Photonic Network-on-Chip
    Wang, Junhui
    Zhu, Ming
    Peng, Chao
    Zhou, Lewen
    Qian, Yue
    Dou, Wenhua
    [J]. 2014 THIRD INTERNATIONAL CONFERENCE ON E-TECHNOLOGIES AND NETWORKS FOR DEVELOPMENT (ICEND), 2014, : 127 - 130
  • [28] A circuit-switched network architecture for network-on-chip
    Liu, J
    Zheng, LR
    Tenhunen, H
    [J]. IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2004, : 55 - 58
  • [29] HiWA: A Hierarchical Wireless Network-on-Chip Architecture
    Rezaei, Amin
    Safaei, Farshad
    Daneshtalab, Masoud
    Tenhunen, Hannu
    [J]. 2014 INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING & SIMULATION (HPCS), 2014, : 499 - 505
  • [30] NoCGuard: A Reliable Network-on-Chip Router Architecture
    Shafique, Muhammad Akmal
    Baloch, Naveed Khan
    Baig, Muhammad Iram
    Hussain, Fawad
    Zikria, Yousaf Bin
    Kim, Sung Won
    [J]. ELECTRONICS, 2020, 9 (02)