A Sub-1V Low Dropout Regulator with Improved Transient Performance for Low Power Digital Systems

被引:0
|
作者
Jiang, Y. S. [1 ]
Wang, D. [1 ]
Chan, P. K. [1 ]
机构
[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore, Singapore
关键词
flipped voltage follower; LDO regulator; Miller compensation; output-capacitorless; wide capacitive load range; LDO REGULATOR; VOLTAGE; COMPENSATION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a low-voltage Flipped Voltage Follower (FVF) based output-capacitorless low-dropout (OCL-LDO) regulator. It consists of a transient-enhanced push-pull (TEPP) driving stage to improve the response at low quiescent power. With simple Miller compensation (SMC) and modified damping factor control (DFC) compensation, the regulator permits small compensation capacitance for maintaining circuit stability under different loading conditions whilst increasing the design flexibility. Validated by UMC 65nm CMOS technology, the regulator can support the capacitive load from 100 pF to 3 nF. It delivers a maximum load current of 10 mA with a dropout voltage of 200 mV in 0.9 V supply and a quiescent current of less than 20 A. The regulator's output voltage stays within 1% of the final steady-state voltage level during load current transitions. Compared with other reported counterparts, it displays reasonable good transient figure-of-merits (FOMs), particularly suitable for low power digital systems.
引用
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页码:29 / 32
页数:4
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