An Analog Front-end ASIC Design for 16-channel SiPM Readout in PET Detectors

Time over dynamic threshold (TODT) has been proven to be an effective method in our previous work for nuclear energy signal digitizing. Comparing with other time over threshold (TOT) methods, TODT can translate the amplitude of nuclear pulses into time width with strict linearity, large measurement dynamic range, and high signal-to-noise ratio. Since high-speed comparators and multi-channel time-to-digital converters (TDCs) can be realized in commercialized field programmable gate array (FPGA) chips, FPGA-based TODT is favored for PET scanners in laboratories. However, a PET detector normally has 64 SiPM readout channels, the analog circuit before the TODT-FPGA chip should be implemented in an ASIC. We have designed this analog front-end ASIC chip which reads out the timing signals and energy signals of 16-channel SiPMs for the followed TODT-FPGA chip. The ASIC chip was tapped out with CMOS180 process, and a performance evaluation board combining the ASIC and TODT-FPGA was constructed. Using a PET detector (LYSO crystal coupled with a Hamamatsu S13361 SiPM) and a coincidence detector (LaBr3 crystal coupled with PMT R9800), the coincidence time resolution was measured as 219.2 ps, and the energy resolution for Na-22 source was measured as 12.5%. This preliminary test results show that the common-gate circuit for timing readout and the charge integral circuit for energy readout are effective. The architecture of an analog front-end ASIC coupled with a TODT-FPGA for PET detectors can largely simplify the chip design. The advantages of short time-to-market and flexible design of data processing and interfaces are also demonstrated.