Challenges for Advanced End of the Roadmap, Beyond Si and Beyond CMOS Technologies

被引：0

作者：

Claeys, C. ^{[1
,2
]}

Simoen, E. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Katholieke Univ Leuven, EE Dept, Leuven, Belgium

来源：

2017 32ND SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO): CHIP ON THE SANDS | 2017年

关键词：

FinFETs; TFETs; nanowires; retention time; 2D materials; heterogeneous integration; spintronics; neuromorphic computing; FIELD-EFFECT-TRANSISTORS; 2-DIMENSIONAL MATERIALS; INTEGRATION; SILICON; DEVICE; POLARIZATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Future technologies put stringent demands on materials, process modules and device architectures. Design considerations favor the future use of vertical devices like tunnelFETs and nanowires. Heterogenous integration of Ge and III-V technologies on a silicon platform enables to fabricate System-on-Chip applications, while increased functionality is achieved by 3D integration. Attention is also given to the trend and progress in the use of 2D material and devices, spintronics and neuromorphic computing.

引用

页数：6

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