On-die PDN Design and Analysis for Minimizing Power Supply Noise

被引：0

作者：

Otsuka, Hiroki ^{[1
]}

Kubo, Genki ^{[1
]}

Kobayashi, Ryota ^{[1
]}

Mido, Tatsuya ^{[1
]}

Kobayashi, Yoshinori ^{[1
]}

Fujii, Hideyuki ^{[1
]}

Sudo, Toshio ^{[1
]}

机构：

[1] Shibaura Inst Technol, Koto Ku, Tokyo 108, Japan

来源：

2012 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS) | 2012年

关键词：

CIRCUITS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Power integrity design is a critical issue for advanced CMOS LSIs which operate at higher clock frequency and at lower supply voltage. Power supply fluctuation excited by core circuits or I/O buffer circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be designed as low as possible in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN created by the parallel combination of on-chip capacitance and package inductance induce the unwanted power supply fluctuation. In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adjusting different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

引用

页码：17 / 20

页数：4

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