Fault-memory handling for hardware-accelerated concurrent fault simulation

From the view of product-testing, fault simulation of VLSI circuits is a necessity. Algorithms in use are single fault propagation, parallel fault simulation, and concurrent fault simulation, where the last one is the most effective one. The drawback, however, is that the amount of fault effects to be stored during a simulation step varies from design to design in a very wide range. The amount of fault effects even may exhaust the memory capacity available for fault effect handling. A standard solution is to employ a multiple-pass-algorithm by partitioning the set of faults to be considered. Then, partition after partition is simulated. Beyond known, but insufficient partitioning strategies, that only take into account the type of faults, stuck-at-0, stuck-at-1, and the location type, input 0, input 1,..., output, this paper offers a solution based on additionally partitioning the design graph due to preestimating the flow of fault effects. The effect on simulation performance is shown.