A CMOS D-band Low Noise Amplifier with 22.4 dB Gain and a 3 dB Bandwidth of 16 GHz for Wireless Chip to Chip Communication

This paper presents a D-band six-stage low noise amplifier design in 65 nm CMOS process. The single stage amplifier consists of combined cascode topology and common source topology to achieve high gain and save power consumption. For a high-data rate communication system, the wideband characteristic is very important. In order to enhance the 3 dB bandwidth, a two-center frequency technique and inductive feedback technique are used. The odd and even stages are designed to operate at 115 GHz and 125 GHz, respectively. In addition, the amplifier was realized by a conjugate matching technique to achieve low-loss between each stage. The measured results show that the low noise amplifier can provide a gain of 22.4 dB with a 3 dB bandwidth of 16 GHz. The measured OP1 dB is -4.5 dBm at 120 GHz. The minimum noise figure was 11.4 dB at 117 GHz. The core chip size is 980 x 200 m(2) and the power consumption of the proposed low noise amplifier is 61 mW at a supply voltage of 1.7 V. To the authors' knowledge, this is the best performance (gain -3 dB bandwidth product) with low power consumption in 65 nm CMOS at D-band frequency.