A multi-cycle fixed point square root module for FPGAs

被引：8

作者：

Martin del Campo, Fernando ^{[1
]}

Morales-Reyes, Alicia ^{[1
]}

Perez-Andrade, Roberto ^{[3
]}

Cumplido, Rene ^{[1
]}

Orozco-Lugo, Aldo G. ^{[2
]}

Feregrino, Claudia ^{[1
]}

机构：

[1] INAOE, Dept Comp Sci, Puebla, DF, Mexico

[2] CINVESTAV IPN, Dept Elect Engn, Mexico City, DF, Mexico

[3] CINVESTAV IPN, Informat Technol Lab, Tamps, Mexico

来源：

IEICE ELECTRONICS EXPRESS | 2012年 / 9卷 / 11期

关键词：

Square root; non-restoring algorithm; FPGA; IMPLEMENTATIONS; ALGORITHM;

D O I：

10.1587/elex.9.971

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a module that solves the square root by obtaining a number of more significant bits from a look-up table as an approximate root. A set of possible roots are then appended and squared for comparison to the original radicand, finely tuning the calculation. The module stops as soon as it finds an exact root, therefore not all entries take the same number of cycles, reducing the number of iterations required for full resolution. The proposed FPGA module overcomes a Xilinx's logiCORE IP in terms of resources utilization and in several cases latency due to its flexible structure configuration.

引用

页码：971 / 977

页数：7

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