A Custom Reconfigurable Power Efficient FIR Filter

被引：0

作者：

Sakthivel, R. ^{[1
]}

Mishra, Ishita ^{[2
]}

Jalke, Vrushali ^{[2
]}

Wachaspati, Asmita ^{[2
]}

机构：

[1] VIT Univ, SENSE, Sch Elect & Elect, Vellore, Tamil Nadu, India

[2] VIT Univ, SENSE, Sch Elect & Elect, VLSI Design, Vellore, Tamil Nadu, India

来源：

PROCEEDINGS OF IEEE INTERNATIONAL CONFERENCE ON CIRCUIT, POWER AND COMPUTING TECHNOLOGIES (ICCPCT 2016) | 2016年

关键词：

RAG-n; Multiplier-less; FIR filter; DSP system; DIGITAL-FILTERS;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Power consumption is the most crucial point of designing any architecture. Till the date so many techniques have been discussed for realizing Digital filters more power efficient. This paper presents a Custom Reconfigurable Power efficient FIR filter which is based on multiplier less configuration using RAG-n algorithm. As multiplier takes the maximum area of any hardware and consumes the highest power so here in this design it is optimized using realizing the multiplier with the help of adder and shifter. FIR filter is symmetrical and has linear phase so stable and easy to implement and supports the number of DSP system. Power analysis shows that the above architecture consumes less power than the traditional one.

引用

页数：4

共 50 条

[41] Reconfigurable FIR Filter Using Distributed Arithmetic on FPGAs
Kumm, Martin
Moeller, Konrad
Zipf, Peter
[J]. 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 2058 - 2061
[42] Power-efficient FIR filter architecture design for wireless embedded system
Lin, SF
Huang, SC
Yang, FS
Ku, CW
Chen, LG
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2004, 51 (01) : 21 - 25
[43] A new hardware efficient, low power FIR digital filter implementation approach
Dabbagh-Sadeghipour, K
Aghagolzadeh, A
[J]. ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2003, : 1144 - 1147
[44] An implementation of area and power efficient digital FIR filter for hearing aid applications
Balaji, V. S.
Upadhyay, Har Narayan
[J]. OPTOELECTRONICS AND ADVANCED MATERIALS-RAPID COMMUNICATIONS, 2015, 9 (5-6): : 657 - 662
[45] An Efficient Block-Based Architecture for Reconfigurable FIR Filter Using Partial-Product Method
Shrivastava, Prabhat Chandra
Kumar, Prashant
Tiwari, Manish
Dhawan, Amit
[J]. CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2022, 41 (04) : 2173 - 2187
[46] An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm
Kalamani, C.
Lekashri, S.
Duraivel, A. N.
Raj, T. Selvin Retna
[J]. AUTOMATIKA, 2024, 65 (01) : 290 - 303
[47] An Efficient Block-Based Architecture for Reconfigurable FIR Filter Using Partial-Product Method
Prabhat Chandra Shrivastava
Prashant Kumar
Manish Tiwari
Amit Dhawan
[J]. Circuits, Systems, and Signal Processing, 2022, 41 : 2173 - 2187
[48] Efficient sparse FIR filter design
Mattera, D
Palmieri, F
Haykin, S
[J]. 2002 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-IV, PROCEEDINGS, 2002, : 1537 - 1540
[49] Low Power and Area Efficient FIR Filter Using Adaptive LMS Algorithm
Dasharatha, M.
Naik, B. Rajendra
Reddy, N. S. S.
[J]. 2017 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), 2017, : 453 - 456
[50] An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications
Kotha, Srinivasa Reddy
Bajaj, Sumit
Kumar, Sahoo Subhendu
[J]. 18TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST, 2014,

← 1 2 3 4 5 →