Architecture of a parallel computer Cenju-4

被引：0

作者：

Kanoh, Y ^{[1
]}

Hirose, T ^{[1
]}

Nakamura, M ^{[1
]}

Hosomi, T ^{[1
]}

Tatsukawa, K ^{[1
]}

Araki, H ^{[1
]}

Sugawara, T ^{[1
]}

Nakata, T ^{[1
]}

机构：

[1] NEC Corp Ltd, C&C Media Res Labs, Miyamae Ku, Kawasaki, Kanagawa 2168555, Japan

来源：

INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS | 1999年

关键词：

D O I：

10.1109/IWIA.1998.779080

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the architecture and the evaluation of a parallel computer Cenju-4. Cenju-4 supports two memory architectures: distribution memory with user-level message passing communication and distribution shared memory with cache-coherent non-uniform memory access (cc-NUMA)feature. Cenju-4 system consists of from 8 to 1024 nodes connected by a multistage network which has multicast, synchronization, and gather functions. Cenju-4 adopts a Mach micro kernel based operating system, which provides several services for parallel processing. We attained 5.5 mu sec communication latency and 168 Mbytes/sec communication throughput in message passing communication.

引用

页码：105 / 113

页数：9

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