Analysis of the NAND-type DRAM-on-SGT for high-density and low-voltage memory.

In this paper, we describe the analysis of the NAND-type DRAM-on-SGT for high-density and low-voltage memory. The cell structure is composed of NAND-type DRAM vertically stacked on an SGT and an SGT-type capacitor. The NAND-structured cell has several NAND-type DRAM-on-SGT cells in series sandwiched between the read select and the ground line. By using this architecture, a cell size of 4F(2) can be achieved. We analyze the dependence of the cell size, the read line capacitance, the cell current and the read line discharge time of the NAND-type DRAM-on-SGT on the number of cells in the NAND-structured cell. When the number (N) of cells in the NAND-structured cell is increased, the cell current is decreased. The cell current when N = 2 and N = 4 are decreased to 69.8% and 44.1% of the cell current when N = 1, respectively. However, when the number of cells connected to one read line remains constant and N is increased, the read line capacitance will decrease because the number of the read select transistors connected to one read line has been reduced. The read line capacitances when N = 2 and N = 4 are decreased to 62.5% and 43.7% of the read line capacitance when N = 1, respectively. The read line discharge times when N = 2 and N = 4 are decreased to 87.1% and 96.4% of the read line discharge time when N = 1, respectively. Therefore, we have shown that the read line discharge time can be minimized when the number of cells in the NAND-structured cell is two. The results of this work can be used as a general guideline in designing the cell array of the NAND-type DRAM-on-SGT.