Application-aware Design Parameter Exploration of NAND Flash Memory

被引:1
|
作者
Bang, Kwanhu
Kim, Dong-Gun [1 ]
Park, Sang-Hoon [2 ]
Chung, Eui-Young [3 ,4 ]
Lee, Hyuk-Jun [5 ]
机构
[1] SK Hynix Inc, R&D Div, Inchon, South Korea
[2] Yonsei Univ, Seoul 120749, South Korea
[3] Samsung Elect, SoC R&D Ctr, Yongin, South Korea
[4] Yonsei Univ, Sch Elect & Elect Engn, Seoul 120749, South Korea
[5] Sogang Univ, Sch Comp Sci & Engn, Seoul, South Korea
基金
新加坡国家研究基金会;
关键词
NAND Flash Memory (NFM); NAND Flash Storage Devices (NFSD); specifications; design parameters;
D O I
10.5573/JSTS.2013.13.4.291
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
NAND flash memory (NFM) based storage devices, e. g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solutions when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research shows that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e. g. request length, update ratios, read-and-modify ratios. Experimental results show that the optimized page and block size can achieve up to 1 5 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM
引用
收藏
页码:291 / 302
页数:12
相关论文
共 50 条
  • [1] Application-aware deduplication for performance improvement of flash memory
    Paik, Joon-Young
    Chung, Tae-Sun
    Cho, Eun-Sun
    DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, 2015, 19 (1-2) : 161 - 188
  • [2] Application-aware deduplication for performance improvement of flash memory
    Joon-Young Paik
    Tae-Sun Chung
    Eun-Sun Cho
    Design Automation for Embedded Systems, 2015, 19 : 161 - 188
  • [3] SRAM Design Exploration with Integrated Application-Aware Aging Analysis
    Listl, Alexandra
    Mueller-Gritschneder, Daniel
    Schlichtmann, Ulf
    Nassif, Sani R.
    2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2019, : 1249 - 1252
  • [4] 3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage
    Matsui, Chihiro
    Takeuchi, Ken
    2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
  • [5] Application-aware adaptive parameter control for LoRaWAN
    Ivoghlian, Ameer
    Wang, Kevin I-Kai
    Salcic, Zoran
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 2022, 166 : 166 - 177
  • [6] RAPID DESIGN EXPLORATION FRAMEWORK FOR APPLICATION-AWARE CUSTOMIZATION OF SOFT CORE PROCESSORS
    Prakash, Alok
    Lam, Siew-Kei
    Singh, Amit Kumar
    Srikanthan, Thambipillai
    FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, : 539 - 542
  • [7] RNFTL: A Reuse-Aware NAND Flash Translation Layer for Flash Memory
    Wang, Yi
    Liu, Duo
    Wang, Meng
    Qin, Zhiwei
    Shao, Zili
    Guan, Yong
    LCTES 10-PROCEEDINGS OF THE ACM SIGPLAN/SIGBED 2010 CONFERENCE ON LANGUAGES, COMPILERS, & TOOLS FOR EMBEDDED SYSTEMS, 2010, : 163 - 172
  • [8] RNFTL: A Reuse-Aware NAND Flash Translation Layer for Flash Memory
    Wang, Yi
    Liu, Duo
    Wang, Meng
    Qin, Zhiwei
    Shao, Zili
    Guan, Yong
    ACM SIGPLAN NOTICES, 2010, 45 (04) : 163 - 172
  • [9] RNFTL: A reuse-aware NAND flash translation layer for flash memory
    Wang, Yi
    Liu, Duo
    Wang, Meng
    Qin, Zhiwei
    Shao, Zili
    Guan, Yong
    ACM SIGPLAN Notices, 2010, 45 (04): : 163 - 172
  • [10] A Workload-Aware-Design of 3D-NAND Flash Memory for Enterprise SSDs
    Sun, Chao
    Soga, Ayumi
    Onagi, Takahiro
    Johguchi, Koh
    Takeuchi, Ken
    PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014), 2015, : 554 - 561