Architecture designs of a large-capacity Abacus ATM switch

The Abacus switch [1] we proposed has size limitation due to excessive routing delay in the switch fabric. Here, we suggest three different approaches to increase the capacity of the Abacus switch to, for instance, 1 Tb/s with existing CMOS technology. The first approach uses a memoryless multi-stage concentration network (MMCN), which I educes the routing delay and increases the capacity of the Abacus switch. The second approach uses a buffered multistage concentration network (BMCN), which uses a funnel concept and an input-buffered concentration modules (CMs) to relax the memory speed constraint. A new priority assignment scheme is proposed for the input-buffered Chi to maintain the cell sequence of a virtual connection. The third approach allows the arbitration cycle exceeding a cell slot and thus resequences cells at the output ports. It is proved that. the maximum degree of out-of-sequence is bounded in the worst case.