IP Over SONET/SDH Link-Layer Processing with Multiprocessor

被引：0

作者：

Zuo, Zhen ^{[1
]}

Liu, Desheng ^{[1
]}

Qin, Jiangyi ^{[1
]}

Huang, Zhiping ^{[1
]}

Su, Shaojing ^{[1
]}

机构：

[1] Natl Univ Def Technol, Coll Mechatron Engn & Automat, Changsha 410073, Hunan, Peoples R China

来源：

INTERNATIONAL JOURNAL OF PATTERN RECOGNITION AND ARTIFICIAL INTELLIGENCE | 2019年 / 33卷 / 04期

关键词：

IP; POS; multiprocessor; FPGA;

D O I：

10.1142/S0218001419580060

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

With the recent increase in IP traffic owing to fiber communication, previous schemes have become inadequate for link-layer processing of IP over SONET/SDH(POS). In this study, a proposal based on m processors to provide mapping or demapping of IP datagrams from or into SONET/SDH is presented, and the value of m is decided based on the link layer rate of POS. Further, the mathematic model of proposed architecture are presented in detail. Then the realization procedures are implemented in a Field-Programmable Gate Array (FPGA). Both theoretical analysis and experimental test prove that the proposed scheme is efficient, portable, cost-efficient and has a lower hardware resources consumption.

引用

页数：16

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