共 50 条
- [2] A 1.9-μm2 loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology [J]. INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, : 643 - 646
- [3] A 0.99-μm2 loadless four-transistor SRAM cell in 0.13-μm generation CMOS technology [J]. 2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 164 - 165
- [4] Development of a load-less CMOS 4-transistor SRAM macro [J]. NEC RESEARCH & DEVELOPMENT, 2001, 42 (01): : 86 - 86
- [5] 4-TRANSISTOR STATIC MEMORY CELL USING CMOS [J]. ELECTRONICS & COMMUNICATIONS IN JAPAN, 1975, 58 (10): : 110 - 118
- [6] Stability analysis of a 400 mV 4-transistor CMOS-SOI SRAM cell operated in subthreshold [J]. 2003 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, 2003, : 247 - 250
- [7] A 4-TRANSISTOR STATIC MEMORY CELL DESIGN WITH A STANDARD CMOS PROCESS [J]. 1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 162 - 166
- [8] SRAM oriented memory sense amplifier design in 0.18μm CMOS technology [J]. 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 145 - 148