共 50 条
- [41] A Low-Power Parasitic-Insensitive Switched-Capacitor Integrator for Delta-Sigma ADCs [J]. 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 986 - 989
- [42] Design of FIR Filters with Sum of Power-of-Two Representation Using Simulated Annealing [J]. 2014 7TH ADVANCED SATELLITE MULTIMEDIA SYSTEMS CONFERENCE AND THE 13TH SIGNAL PROCESSING FOR SPACE COMMUNICATIONS WORKSHOP (ASMS/SPSC), 2014, : 339 - 345
- [43] A low power decimation filter architecture for high-speed single-bit sigma-delta modulation [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1453 - 1456
- [44] Implementation of 1.5V low power two-path decimation filters for communications Δ-Σ converters [J]. 2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS, 2002, : 128 - 131
- [45] A Power-Efficient Polyphase Sharpened CIC Filter for Sigma-Delta ADCs [J]. 2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,
- [46] Signed power-of-two allocation scheme for the design of lattice orthogonal filter banks [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1819 - 1822
- [47] Low power two-stage comb decimation structures for high decimation factors [J]. Analog Integrated Circuits and Signal Processing, 2016, 88 : 245 - 254
- [49] Design of stable 2-D recursive filters using power-of-two coefficients [J]. Proc IEEE Int Conf Electron Circuits Syst, (409-412):
- [50] A sequential reoptimization approach for the design of signed power-of-two coefficient lattice QMF bank [J]. IEEE REGION 10 INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONIC TECHNOLOGY, VOLS 1 AND 2, 2001, : 57 - 60