A Fast H.264 Video Encoder Based on a Digital Signal Processor

被引：1
|
作者：
Wang, Chou-Chen [1 ]
Kao, Jung-Yang [2 ]
Chen, I-An [1 ]
Wang, Hsiang-Chun [1 ]
机构：
[1] I Shou Univ, Dept Elect Engn, Kaohsiung, Taiwan
[2] Ind Technol Res Inst, Informat & Commun Res Labs, Hsinchu, Taiwan
来源：
2014 INTERNATIONAL SYMPOSIUM ON COMPUTER, CONSUMER AND CONTROL (IS3C 2014) | 2014年
关键词：
H.264; DSP; RDO; DMA; PSNR;
D O I：
10.1109/IS3C.2014.311
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, a high-speed H.264 encoder based on a digital signal processor (DSP) is proposed. In order to speed up the process of inter prediction module in H.264 video standard, a fast inter mode decision algorithm (FIMDA) is proposed in this paper. According to the observation of inter prediction mode of any MB and those of its neighbouring blocks from different natural video sequences, we find that there are a high temporal-spatial mode correlation exists in inter mode map of H.264. We exploit the interblock correlation in the inter-mode domain to early terminate the rate-distortion optimization (RDO) calculations. An initial standard compliant raw-C encoder has been optimized in speed for target processor. In addition, the parallelism between algorithm execution and data movement has been fully exploited using DMA. Based on an ADSP-BF548, experimental results show that the proposed FIMDA can achieve time improving ratio (TIR) approximately 31%similar to 62% when compared to the test mode of H.264 (JM 18.1) with insignificant degradation of PSNR.
引用
收藏
页码：1199 / 1202
页数：4
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