A Design Space Comparison of 6T and 8T SRAM Core-Cells

被引：0

作者：

Bauer, Florian ^{[1
,2
]}

Georgakos, Georg ^{[1
]}

Schmitt-Landsiedel, Doris ^{[2
]}

机构：

[1] Infineon Technol AG, Campeon 1, D-85579 Neubiberg, Germany

[2] Tech Univ Munich, D-80290 Munich, Germany

来源：

INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2009年 / 5349卷

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a comparison of 6T and 8T SRAM design spaces for low-power 65 nm and 45 nm CMOS technologies based on simulations using a multi-objective optimization framework. The influence of a bit-line column multiplexer (MUX) on the 8T design space is shown. We demonstrate that 6T and 8T cells show differing area scaling behavior across the whole design space. We identify points on the area-performance trade-off curves that bound regions where either 6T or 8T SRAM cells are optimal.

引用

页码：116 / +

页数：2

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