Opcode encoding for low-power instruction fetch

被引:2
|
作者
Kim, S [1 ]
Kim, J [1 ]
机构
[1] Seoul Natl Univ, Dept Comp Sci, Kwanak Ku, Seoul 151742, South Korea
关键词
D O I
10.1049/el:19990752
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A method for encoding opcodes For low-power instruction Fetching is described. To reduce the switching activity from opcode changes in the instruction fetch logic, opcodes are assigned so that more frequently consecutive instruction pairs have a smaller Hamming distance between their opcodes. The experimental result shows that a switching activity reduction of 37.4 - 66.7% is achievable over a naive encoding method.
引用
收藏
页码:1064 / 1065
页数:2
相关论文
共 50 条
  • [1] Instruction compression and encoding for low-power systems
    Kadayif, I
    Kandemir, MT
    [J]. 15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2002, : 301 - 305
  • [2] Low-power instruction bus encoding for embedded processors
    Petrov, P
    Orailoglu, A
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (08) : 812 - 826
  • [3] Opcode encoding for low power embedded systems
    Pouladi, A
    Nooshabadi, S
    [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 5262 - 5265
  • [4] Low-power BIBITS encoding with register relabeling for instruction bus
    Cheng, CT
    Chiao, WH
    Shann, JJJ
    Chung, CP
    Chen, WF
    [J]. 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papers, 2005, : 41 - 44
  • [5] Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis
    Athanasios, Tziouvaras
    Georgios, Dimitriou
    Georgios, Stamoulis
    [J]. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2022, 19 (02)
  • [6] Low power instruction fetch using profiled variable length instructions
    Collin, M
    Brorsson, M
    [J]. IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2003, : 183 - 188
  • [7] Sensitive Registers: a Technique for Reducing the Fetch Bandwidth in Low-Power Microprocessors
    Robinson, A.
    Garside, J. D.
    [J]. GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, 2007, : 138 - 143
  • [8] A low-power instruction issue queue for microprocessors
    Watanabe, Shingo
    Chiyonobu, Akihiro
    Sato, Toshinori
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2008, E91C (04) : 400 - 409
  • [9] Decomposition of instruction decoders for low-power designs
    Kuo, Wu-An
    Hwang, Tingting
    Wu, Allen C. -H.
    [J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2006, 11 (04) : 880 - 889
  • [10] State encoding for low-power FSMs in FPGA
    Mengibar, L
    Entrena, L
    Lorenz, MG
    Sánchez-Reillo, R
    [J]. INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2003, 2799 : 31 - 40