共 50 条
- [1] PPT: Joint Performance/Power/Thermal Management of DRAM Memory for Multi-Core Systems [J]. ISLPED 09, 2009, : 93 - 98
- [2] Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems [J]. ASPLOS XV: FIFTEENTH INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS, 2010, : 335 - 346
- [4] Fairness via source throttling: A configurable and hgh-performance fairness substrate for multi-core memory systems [J]. ACM SIGPLAN Notices, 2010, 45 (03): : 335 - 346
- [6] Memory performance attacks: Denial of memory service in multi-core systems [J]. USENIX ASSOCIATION PROCEEDINGS OF THE 16TH USENIX SECURITY SYMPOSIUM, 2007, : 257 - 274
- [7] MESS: Memory Performance Debugging on Embedded Multi-core Systems [J]. MODEL CHECKING SOFTWARE, SPIN 2015, 2015, 9232 : 105 - 125
- [8] Modeling and control for thermal balancing of multi-core processors [J]. JOURNAL OF THE FRANKLIN INSTITUTE-ENGINEERING AND APPLIED MATHEMATICS, 2013, 350 (07): : 1836 - 1847
- [9] NBTI Aware Workload Balancing in Multi-core Systems [J]. ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 2009, : 833 - +
- [10] Combine Thread with Memory Scheduling for Maximizing Performance in Multi-core Systems [J]. 2014 20TH IEEE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS), 2014, : 298 - 305