Annealing textures of copper damascene interconnects for ultra-large-scale integration

被引:15
|
作者
Lee, HJ [1 ]
Han, HN
Lee, DN
机构
[1] Seoul Natl Univ, Res Inst Adv Mat, Seoul 151744, South Korea
[2] Seoul Natl Univ, Sch Mat Sci & Engn, Seoul 151744, South Korea
关键词
texture; annealing; copper interconnects; nanostructures;
D O I
10.1007/s11664-005-0156-8
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The annealing textures of copper interconnects depend upon their deposition textures and geometries. The copper interconnects are subjected to tensile stresses even at room temperature, which in turn gives rise to strain energies. The stress distributions in interconnects are not homogeneous due to trenches, resulting in non-fiber-type textures after annealing. To better understand the formation of the non-fiber-type textures, the textures of specimens of 0.2-6 mu m in trench width with 0.2 mu m in space were measured, and the strain energy and stress distributions have been simulated. The simulation results indicate that strain energy density is highest at the upper corners of trench. Therefore, the grain growth rate at the upper corners is fastest, resulting in the {111}< 110 > annealing texture. As the trench width increases, the influence of stresses in the trench increases, even though the strain energy density in the trench is relatively low. In this case the {111}< 112 > component increases, even though the formation of the {111}< 110 > orientation cannot be excluded.
引用
收藏
页码:1493 / 1499
页数:7
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