Highly Stable, Dual-port, Sub-threshold 7T SRAM Cell for Ultra-low Power Application

被引：0

作者：

Sil, Abhijit ^{[1
]}

Bakkamanthala, Srikanth ^{[1
]}

Karlapudi, Swetha ^{[1
]}

Bayoumi, Magdy ^{[1
]}

机构：

[1] Univ Louisiana Lafayette, Ctr Adv Comp Studies, Lafayette, LA 70503 USA

来源：

2012 IEEE 10TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | 2012年

关键词：

NM CMOS; VOLTAGE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As the supply voltage is reducing with feature size, SRAM cell design is going through severe stability issues. The issue becomes worse due to increased variability in below sub-100nm technology. In this paper, we present a highly stable 2-port 7T SRAM cell for ultra-low power in 90nm technology. The dynamic read noise margin is improved by 7X over conventional dual port SRAM. Finally, a 4Kb bit-interleaved SRAM architecture is presented using proposed cell. Experimental results show that memory consumes 1.26pJ/bit at 0.22V supply voltage with 2MHz performance. The dynamic read noise margin is improved by 7X over conventional dual port SRAM. The successful write and read operations can be performed at supply voltage as low as 0.17V. Two level write decoder architecture is used to eliminate the pseudo read problem in unselected columns.

引用

页码：493 / 496

页数：4

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