Interconnect Solutions for Virtualized Field-Programmable Gate Arrays

Contemporary datacenters are enhancing their compute capacity, power efficiency, and processing latency by integrating field-programmable gate arrays (FPGA). One would like to virtualize FPGAs to share them between multiple users and to be able to allocate incoming tasks to FPGAs without interrupting their operation. To virtualize FPGAs, their complexities, such as board-specific system-level integration and tricky I/O timing closure problems should be abstracted away from users. To this end FPGA designers have proposed the shell concept which abstracts away the board-specific details from the user and provides an easy-to-use interface to the user application. In this paper, we create several shells using a wide variety of interconnect solutions and rigorously evaluate them in terms of accelerator frequency, usable bandwidth, area-efficiency, latency, wire demand, and FPGA routing congestion. We show that virtualization of four accelerators per chip with traditional bus-based FPGA interconnect costs an average frequency drop of 24%, increases the wire demand of the shell to 2.78X, and creates significant routing congestion. We also show that while FPGA-optimized soft network on chip interconnect solutions can mitigate the reduction in accelerator frequency, they exacerbate the wire demand and routing congestion problems and offer a lower usable bandwidth. Finally, we demonstrate that hard networks on chip are a superior interconnect solution for virtualized FPGAs in all of the aforementioned evaluation criteria making them well-suited to datacenter-optimized FPGAs.