A 2.5-Gb/s clock and data recovery circuit with a 1/4-rate linear phase detector

被引：0

作者：

Alavi, SM ^{[1
]}

Shoaei, A ^{[1
]}

机构：

[1] Univ Tehran, IC Design Ctr, ECE Dept, Tehran, Iran

来源：

17th ICM 2005: 2005 International Conference on Microelectronics, Proceedings | 2005年

关键词：

clock and data recovery; SONET; OC-48; linear phase detector; voltage-controlled oscillator (VCO); 1/4-rate clock;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 2.5-Gb/s phase-lock clock and data recovery (CDR) circuit is proposed in system simulation for SONET OC-48 (2.488/2.666-Gb/s) transceiver applications. The CDR circuit exploits 1/4 - rate linear phase detector. Making using of this technique the design of voltage controlled oscillator (VCO) facilitates and also it eliminates 1:4 demultiplexer and frequency divider since this topology directly produces recover data.

引用

页码：59 / 62

页数：4

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