Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit

This paper presents a fine-grain cell design for a Multiple-Valued (MV) reconfigurable VISI using a single Differential-Pair Circuit (DPC). The VLSI involves a bitserial localized data transfer architecture. The cell consists of a Multiple-Valued Source-Coupled Logic (MVSCL)-based threshold logic gate, a dynamic latch and a switch block. The threshold logic gate consists of only one universal comparator A single DPC is used as a component of the universal comparator. By using programmable current sources for the DPC. the driving capability of the cell and the weight of the output can be changed according to the reconfigured information. The DPC compares a multiple-valued (MV) input with a threshold which is provided by a programmable threshold voltage generator. This leads to the high utilization of the cell because almost all the universal comparators in the VLSI chip can be utilized effectively without idle states. Furthermore, fine-grain pipelining increases the throughput by the VLSL. The VLSI is designed using 0.18 mu m CMOS standard design rule. HSPICE simulation results show that, the throughput and the lower consumption are greatly improved in comparison with the equivalent VLSI reported until now.