A High-Speed DDFS MMIC with Frequency, Phase and Amplitude Modulations in 65nm CMOS

被引：0
|
作者：
Alonso, Abdel Martinez [1 ]
Miyahara, Masaya [1 ]
Matsuzawa, Akira [1 ]
机构：
[1] Tokyo Inst Technol, Dept Elect & Elect Engn, Meguro Ku, 2-12-1-S3-27 Ookayama, Tokyo 1528552, Japan
来源：
2017 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2017年
关键词：
High-speed DDFS; CMOS; FM; PM; AM;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a digital-mapping DDFS with a frequency tuning and amplitude resolutions of 24-bits and 10-bits respectively. This Si-CMOS-MMIC is the first solution supporting a sampling rate of 7GS/s and frequency, phase and amplitude modulations in the digital domain. It includes a 14-bits pipelined ripple-carry adder and a 10-bits high-speed multiplier for phase and amplitude modulations respectively. The worst case wideband/narrowband SFDR is 32dBc/42dBc. This system consumes 85.9mW/(GS/s) from a 1.2V power supply when the amplitude/phase modulations are enabled, resulting in a FoM of 469.6GS/s.2((SFDR/6))/W. A proof-of-concept chip with an active area of 0.23mm(2) was characterized in LQFP packages.
引用
收藏
页码：181 / 184
页数：4
相关论文
共 50 条
  • [21] 65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application
    Fung, SKH
    Huang, HT
    Cheng, SM
    Cheng, KL
    Wang, SW
    Wang, YP
    Yao, YY
    Chu, CM
    Yang, SJ
    Liang, WJ
    Leung, YK
    Wu, CC
    Lin, CY
    Chang, SJ
    Wu, SY
    Nieh, CF
    Chen, CC
    Lee, TL
    Jin, Y
    Chen, SC
    Lin, LT
    Chiu, YH
    Tao, HJ
    Yu, CF
    Jang, SM
    Yu, KF
    Wang, CH
    Ong, TC
    See, YC
    Diaz, CH
    Liang, MS
    Sun, YC
    2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2004, : 92 - 93
  • [22] Low power High-speed 10 Gb/s 4:1 Multiplexer for Sliding-IF digital Centric Transmitter in 65nm CMOS
    Bousseaud, Pierre
    Negra, Renato
    2016 GERMAN MICROWAVE CONFERENCE (GEMIC), 2016, : 349 - 352
  • [23] High-speed CMOS frequency divider
    Chen, RY
    ELECTRONICS LETTERS, 1997, 33 (22) : 1864 - 1865
  • [24] Implement of Two New High-Speed Low-Power PFDs with Low Blind Zone and Dead Zone in 65nm CMOS Technology
    Ghasemian, Hossein
    Bahrami, Amin
    Jamadi, Behdad
    Abiri, Ebrahim
    Salehi, Mohammad Reza
    2020 28TH IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE), 2020,
  • [25] High-speed CMOS frequency divider
    Nantai Inst of Technology, Tainan, Taiwan
    Electron Lett, 22 (1864-1865):
  • [26] High performance 30nm bulk CMOS for 65nm technology node(CMOS5)
    Morifuji, E
    Kanda, M
    Yanagiya, N
    Matsuda, S
    Inaba, S
    Okano, K
    Takahashi, K
    Nishigori, M
    Tsuno, H
    Yamamoto, T
    Hiyama, K
    Takayanagi, M
    Oyamatsu, H
    Yamada, S
    Noguchi, T
    Kakumu, M
    INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 655 - 658
  • [27] A 57-78 GHz Frequency Tripler MMIC in 65-nm CMOS
    Lee, You-Tang
    Hsiao, Yuan-Hung
    Wang, Huei
    IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2016, 26 (09) : 723 - 725
  • [28] A Wideband Injection Locking Scheme and Quadrature Phase Generation in 65nm CMOS
    Raj, Mayank
    Emami-Neyestanak, Azita
    2013 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC), 2013, : 261 - 264
  • [29] Low-Leakage and Low-Power Implementation of High-Speed 65nm Logic Gates
    Wu, Tsung-Yi
    Lu, Liang-Ying
    Liang, Cheng-Hsun
    EDSSC: 2008 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, 2008, : 37 - 40
  • [30] High performance 25 nm gate CMOSFETs for 65nm node high speed MPUs
    Goto, K
    Tagawa, Y
    Ogta, H
    Morioka, H
    Pidin, S
    Momiyama, Y
    Kokura, Y
    Inagaki, S
    Tamura, N
    Hori, M
    Mori, T
    Kase, M
    Hashimoto, K
    Kojima, M
    Sugii, T
    2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, : 623 - 626
12345