Field programmable gate array based parallel matrix multiplier for 3D affine transformations

被引:3
|
作者
Bensaali, F.
Amira, A.
机构
[1] Univ Hertfordshire, Sch Elect Commun & Elect Engn, Hatfield AL10 9AB, Herts, England
[2] Brunel Univ, Sch Engn & Design, Uxbridge UB8 3PH, Middx, England
来源
关键词
D O I
10.1049/ip-vis:20045076
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, computer aided design or visualisation applications. This article investigates the suitability of field programmable gate array devices as an accelerator for implementing 3D affine transformations. Proposed solution based on processing large matrix multiplication have been implemented, for large 3D models, on the RC1000 Celoxica board based development platform using Handel-C. Outstanding results have been obtained for the acceleration of 3D transformations using fixed and floating-point arithmetic.
引用
收藏
页码:739 / 746
页数:8
相关论文
共 50 条
  • [1] Design optimisation of multiplier-free parallel pipelined FFT on field programmable gate array
    Godi, Prasanna Kumar
    Krishna, Battula Tirumala
    Kotipalli, Pushpa
    IET CIRCUITS DEVICES & SYSTEMS, 2020, 14 (07) : 995 - 1000
  • [2] Vector Matrix Multiplier on Field Programmable Analog Array
    Schlottmann, Craig
    Petre, Csaba
    Hasler, Paul
    2010 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, 2010, : 1522 - 1525
  • [3] Field Programmable Gate Array Implementation of Reversible Binary Coded Decimal Multiplier
    Devi, S. Sharmila
    Bhanumathi, V.
    Aruna, T. Abiseha
    JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2024, 19 (10) : 1053 - 1062
  • [4] An FPGA based coprocessor for 3D affine transformations
    (Institute of Electrical and Electronics Engineers Inc., United States):
  • [5] An FPGA based coprocessor for 3D affine transformations
    Bensaali, F
    Amira, A
    Bouridane, A
    2003 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS, 2003, : 288 - 291
  • [6] Implementation of dynamic matrix control on field programmable gate array
    Lan J.
    Li D.-W.
    Yang N.
    Xi Y.-G.
    Journal of Shanghai Jiaotong University (Science), 2011, 16 (4) : 441 - 446
  • [7] Implementation of Dynamic Matrix Control on Field Programmable Gate Array
    兰建
    李德伟
    杨楠
    席裕庚
    JournalofShanghaiJiaotongUniversity(Science), 2011, 16 (04) : 441 - 446
  • [8] Design of field programmable gate array based real-time Double-precision floating-point matrix multiplier
    Institute of Advanced Digital Technologies and Instrumentation, Zhejiang University, Hangzhou 310027, China
    不详
    Zhejiang Daxue Xuebao (Gongxue Ban), 2008, 9 (1611-1615):
  • [9] Field programmable gate array based reconfigurable preprocessor
    Box, Brian
    1994, : 40 - 48
  • [10] An FPGA implementation of 3D affine transformations
    Bensaali, F
    Amira, A
    Uzun, IS
    Ahmedsaid, A
    ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2003, : 715 - 718