An FPGA implementation of 3D affine transformations

被引：0

作者：

Bensaali, F ^{[1
]}

Amira, A ^{[1
]}

Uzun, IS ^{[1
]}

Ahmedsaid, A ^{[1
]}

机构：

[1] Queens Univ Belfast, Sch Comp Sci, Belfast BT7 1NN, Antrim, North Ireland

来源：

ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, Computer Aided Design (CAD) or visualization applications. This paper investigates the suitability of Field Programmable Gate Array (FPGA) devices as a low cost solution for implementing 3D affine transformations. A proposed solution based on processing large matrix multiplication has been implemented, for large 3D models, on the RC1000-PP Celoxica board based development platform using Handel-C, a C-like language supporting parallelism, flexible data size and compilation of high-level programs directly into FPGA hardware.

引用

页码：715 / 718

页数：4

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