A CMOS voltage comparator with rail-to-rail input-range

被引：13

作者：

Chu, WS ^{[1
]}

Current, KW ^{[1
]}

机构：

[1] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 1999年 / 19卷 / 02期

关键词：

CMOS continuous-time voltage comparator; rail-to-rail input range;

D O I：

10.1023/A:1008349731160

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A simple new continuous-time CMOS comparator circuit with rail-to-rail input common-mode range and rail-to-rail output is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit has been realized in an area of 416 mu m x 221 mu m in a MOSIS 2-micron CMOS technology. Average delay of about 63 ns has been measured at 3 V (1.3 mA), and about 89 ns at 5 V (1.1 mA).

引用

页码：145 / 149

页数：5

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