Implement based on FPGA of Bit Error Rate Tester

被引：0

作者：

Liu, L ^{[1
]}

Mei, X ^{[1
]}

Li, S ^{[1
]}

机构：

[1] Beijing Jiaotong Univ, Sch Elect & Informat Engn, Beijing 100044, Peoples R China

来源：

ICEMI 2005: CONFERENCE PROCEEDINGS OF THE SEVENTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOL 2 | 2005年

关键词：

bit error rate tester; FPGA and MCU;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Bit Error Rate Tester (BERT) is capable of meeting the most stringent error performance requirements Of digital transmission facilities. In this paper, a viable way is brought forward to design a BERT with FPGA and MCU.

引用

页码：129 / 133

页数：5

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