Reliability study of high-density EBGA packages using the Cu metallized silicon

被引:3
|
作者
Yang, Liyu [1 ]
Bemstein, Joseph [2 ]
机构
[1] Freescale Semicond Inc, Chandler, AZ 85224 USA
[2] Univ Maryland, Dept Mech Engn, College Pk, MD 20742 USA
关键词
die cracking; failure rate; reliability; thin film delamination; wafer sawing;
D O I
10.1109/TCAPT.2008.922004
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The reliability of high-density enhanced ball grid array (EBGA) packages using the eight-layer Cu metallization silicon was discussed. The key failure mechanisms included the die cracking (in the vicinity of the edge) and thin film delamination. It was noticed that the failure was unique to the Cu metallization silicon. The large package body size (45 mm(2)) and the die size (approximately 15 mm(2)) provided additional manufacturing and reliability challenges. The die-edge defects induced during the wafer sawing process were exhibited to be the culprits of the die cracking and the thin film delamination failures. Additionally, the height of die attach fillets significantly influenced the stresses on the die edge, and the excessive fillet height was found to help extend initial cracks at the edge of the silicon. The results demonstrated the adoption of a dual-step wafer sawing scheme and resin blades would control the defects and reduce the failure rate dramatically. A mixture of low-stress encapsulation and die attach materials would help improve the overall reliability of the packages as well. The solder joint reliability of the package was very robust based on the board-level reliability testing results. The statistical analysis of the test results confirmed that most of the die cracking and thin film delamination failures were early-life failures and random. A good sample screening scheme and the process improvement procedure would help improve the reliability and insure the customer a low failure rate for the lifetime of the product. The predicted reliability of the package met the application life needs for the products with process improvement plans in place.
引用
收藏
页码:702 / 711
页数:10
相关论文
共 50 条
  • [41] A Study on High-density High-speed SerDes Design in Buildup Flip Chip Ball Grid Array Packages
    Xiang, Gordon
    Sheach, Keith
    Brunet, Pierre
    2009 EUROPEAN MICROELECTRONICS AND PACKAGING CONFERENCE (EMPC 2009), VOLS 1 AND 2, 2009, : 248 - 251
  • [42] RELIABILITY EVALUATION OF ALUMINUM-METALLIZED MOS DYNAMIC RAMS IN PLASTIC PACKAGES IN HIGH HUMIDITY AND TEMPERATURE ENVIRONMENTS
    STRINY, KM
    SCHELLING, AW
    IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1981, 4 (04): : 476 - 481
  • [43] Selective silicon nanoparticle growth on high-density arrays of silicon nitride
    Coffee, Shawn S.
    Shahrjerdi, Davood
    Banerjee, Sanjay K.
    Ekerdt, John G.
    JOURNAL OF CRYSTAL GROWTH, 2007, 308 (02) : 269 - 277
  • [45] Formation of high-density silicon dots on a silicon-on-insulator substrate
    Tabe, M
    Kumezawa, M
    Yamamoto, T
    Makita, S
    Yamaguchi, T
    Ishikawa, Y
    APPLIED SURFACE SCIENCE, 1999, 142 (1-4) : 553 - 557
  • [46] Printed wiring board design adopts aramid, enables high-density packages
    Anon
    JEE. Journal of electronic engineering, 1995, 32 (338): : 42 - 43
  • [47] Failure analysis of lead-free solder joints for high-density packages
    Lau, J
    Shangguan, DK
    Castello, T
    Horsley, R
    Smetana, J
    Hoo, N
    Dauksher, W
    Love, D
    Menis, I
    Sullivan, B
    SOLDERING & SURFACE MOUNT TECHNOLOGY, 2004, 16 (02) : 69 - 76
  • [48] Design, materials and process for lead-free assembly of high-density packages
    Smetana, J
    Horsley, R
    Lau, J
    Snowdon, K
    Shangguan, D
    Gleason, J
    Memis, I
    Love, D
    Dauksher, W
    Sullivan, B
    SOLDERING & SURFACE MOUNT TECHNOLOGY, 2004, 16 (01) : 53 - 62
  • [49] FATIGUE BEHAVIOR OF HIGH-DENSITY SILICON-NITRIDE
    KOSSOWSKY, R
    AMERICAN CERAMIC SOCIETY BULLETIN, 1972, 51 (04): : 430 - +
  • [50] Silicon Optical Interposers for High-Density Optical Interconnects
    Urino, Yutaka
    Nakamura, Takahiro
    Arakawa, Yasuhiko
    SILICON PHOTONICS III: SYSTEMS AND APPLICATIONS, 2016, 122 : 1 - 39