Fully back-end TSV process by Cu electro-less plating for 3D smart sensor systems

被引:13
|
作者
Santagata, F. [1 ]
Farriciello, C. [1 ]
Fiorentino, G. [1 ]
van Zeijl, H. W. [1 ]
Silvestri, C. [1 ]
Zhang, G. Q. [1 ]
Sarro, P. M. [1 ]
机构
[1] Delft Univ Technol, Dept Microelect, NL-2628 CT Delft, Netherlands
关键词
HIGH-ASPECT-RATIO; BOTTOM-UP FILL; SEED LAYERS; COPPER; SILICON; DEPOSITION; HOLES;
D O I
10.1088/0960-1317/23/5/055014
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A fully back-end process for high-aspect ratio through-silicon vias (TSVs) for 3D smart sensor systems is developed. Atomic layer deposition of TiN provides a highly conformal barrier as well as a seed layer for metal plating. Cu electro-less plating on the chemically activated TiN surfaces is applied to uniformly fill the TSVs in a significantly shorter time (2 h for 300 mu m deep and 20 mu m wide TSVs) than with Cu bottom-up electroplating (>20 h). The process is CMOS compatible and can be performed after the last metalization step, making it a fully back-end process (VIA-last approach). Wafers containing metal interconnections on both sides are in fact used as demonstrator. Four-terminal 3D Kelvin structures are fabricated and characterized. An average resistance value of 650 m Omega is measured for 300 mu m deep TSVs with an aspect ratio of 15. The crosstalk between adjacent TSVs is also measured by means of S-parameters characterization on dedicated RF test structures. The closest TSVs (75 mu m) show a reciprocal crosstalk of less than -20 dB at 30 GHz.
引用
收藏
页数:10
相关论文
共 18 条
  • [1] Fully Back-end TSV Process by Cu Electro-less Plating for 3D Smart Sensor Systems
    Santagata, F.
    Fiorentino, G.
    Nie, M.
    Farriciello, C.
    Poelma, R.
    Zhang, G. Q.
    Sarro, P. M.
    Nie, M.
    [J]. 2012 IEEE SENSORS PROCEEDINGS, 2012, : 668 - 671
  • [2] High density, low leakage Back-End 3D capacitors for mixed signals applications
    Detalle, M.
    Barrenetxea, M.
    Muller, P.
    Potoms, G.
    Phommahaxay, A.
    Soussan, P.
    Vaesen, K.
    De Raedt, W.
    [J]. MICROELECTRONIC ENGINEERING, 2010, 87 (12) : 2571 - 2576
  • [3] High performances 3D damascene MIM capacitors integrated in copper back-end technologies
    Cremer, S.
    Richard, C.
    Benoit, D.
    Besset, C.
    Manceau, J-P
    Farcy, A.
    Perrot, C.
    Segura, N.
    Marin, M.
    Becu, S.
    Boret, S.
    Thomas, M.
    Guillaumet, S.
    Bonnard, A.
    Delpech, P.
    Bruyere, S.
    [J]. PROCEEDINGS OF THE 2006 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2006, : 259 - +
  • [4] Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET
    Shi-Xian Guan
    Tilo H. Yang
    Chih-Hao Yang
    Chuan-Jie Hong
    Bor-Wei Liang
    Kristan Bryan Simbulan
    Jyun-Hong Chen
    Chun-Jung Su
    Kai-Shin Li
    Yuan-Liang Zhong
    Lain-Jong Li
    Yann-Wen Lan
    [J]. npj 2D Materials and Applications, 7
  • [5] Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET
    Guan, Shi-Xian
    Yang, Tilo H. H.
    Yang, Chih-Hao
    Hong, Chuan-Jie
    Liang, Bor-Wei
    Simbulan, Kristan Bryan
    Chen, Jyun-Hong
    Su, Chun-Jung
    Li, Kai-Shin
    Zhong, Yuan-Liang
    Li, Lain-Jong
    Lan, Yann-Wen
    [J]. NPJ 2D MATERIALS AND APPLICATIONS, 2023, 7 (01)
  • [6] Low-Cost TSV Process Using Electroless Ni Plating for 3D Stacked DRAM
    Kawano, Masaya
    Takahashi, Nobuaki
    Komuro, Masahiro
    Matsui, Satoshi
    [J]. 2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, : 1094 - 1099
  • [7] Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging
    Ibrahim, Aya
    Zhang, Shuping
    Angiolini, Federico
    Arditi, Marcel
    Kimura, Shinji
    Goto, Satoshi
    Thiran, Jean-Philippe
    De Micheli, Giovanni
    [J]. IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, 2018, 12 (05) : 968 - 981
  • [8] Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform
    Pozder, S
    Lu, JQ
    Kwon, Y
    Zollner, S
    Yu, J
    McMahon, JJ
    Cale, TS
    Yu, K
    Gutmann, RJ
    [J]. PROCEEDINGS OF THE IEEE 2004 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2004, : 102 - 104
  • [9] Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration
    Chiang, Cheng-Hao
    Hu, Yu-Chen
    Chen, Kuo-Hua
    Chiu, Chi-Tsung
    Chuang, Ching-Te
    Hwang, Wei
    Chiou, Jin-Chern
    Tong, Ho-Ming
    Chen, Kuan-Neng
    [J]. 2012 7TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2012,
  • [10] Effect of Electro(less) Plating on Mechanical and Geometric Properties of Polymer-metal Structures Based on 3D Printed Models
    Tucek, Radek
    Vojtech, Lukas
    [J]. 2024 47TH INTERNATIONAL SPRING SEMINAR ON ELECTRONICS TECHNOLOGY, ISSE 2024, 2024,