Real Time Iris Segmentation on FPGA

被引:0
|
作者
Ngo, Hau [1 ]
Shafer, Jennifer [1 ]
Ives, Robert [1 ]
Rakvic, Ryan [1 ]
Broussard, Randy [2 ]
机构
[1] USN Acad, Dept Elect & Comp Engn, Annapolis, MD 21402 USA
[2] USN Acad, Weap & Syst Engn Dept, Annapolis, MD 21402 USA
关键词
iris segmentation; iris recognition; Canny edge detection; on-chip buffering; pipeline and parallel architecture; FPGA-based real time processing;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a real time FPGA-based iris segmentation system is presented. The segmentation method implements the Canny edge detection algorithm and a circle search to detect an iris in an image or video frame. The proposed high performance architecture utilizes on-chip memory to significantly improve the throughput of the pipelined and parallel structure. A data forwarding technique is incorporated in the design to efficiently utilize the FPGA's embedded resources. The proposed architecture demonstrates a high speed processing capability that will facilitate the use of dedicated hardware to support an iris recognition application for large databases.
引用
收藏
页码:1 / 7
页数:7
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