Efficient Successive Cancellation Decoder for Polar Codes Based on Frozen Bits

被引：0

作者：

Piao, Zheyan ^{[1
]}

Kim, Yeon-Jin ^{[1
]}

Chung, Jin-Gyun ^{[1
]}

机构：

[1] Chonbuk Natl Univ, Div Elect Engn, Jeonju, South Korea

来源：

2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) | 2016年

关键词：

polar code; frozen bit; low latency; low area; ARCHITECTURES;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Recently, polar codes have received much attention due to their simple structure and low decoding complexity. However, because of the long decoding latency, polar codes are still not suitable for real-time applications. In this paper, by the analysis of the position of frozen bits and the architecture of conventional SC decoder, we present an efficient SC decoder architecture. Using the proposed architecture, the decoding latency of a polar code with length N can be reduced from N-1 to N/2-1. Also, the proposed architecture can reduce the number of MPEs about 33% compared with conventional SC decoder.

引用

页码：585 / 587

页数：3

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