A 60 GHz PLL Synthesizer with an Injection Locked Frequency Divider using a Fast VCO Frequency Calibration Algorithm

被引：0
|
作者：
Shima, Takahiro [1 ]
Miyanaga, Kenji [1 ]
Takinami, Koji [1 ]
机构：
[1] Panasonic Corp, Sensor Devices Dev Off, Device Solut Ctr, Tsuzuki Ku, Yokohama, Kanagawa 2248539, Japan
来源：
2012 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC 2012) | 2012年
关键词：
Phase locked loop; synthesizer; injection locked frequency divider; locking range; calibration;
D O I：
暂无
中图分类号：
TN [电子技术、通信技术];
学科分类号：
0809 ;
摘要：
A 60 GHz phase-locked loop (PLL) synthesizer with an injection locked frequency divider (ILFD) is presented. The PLL employs a simple and fast calibration algorithm consisting of the VCO sub-band selection and the adjustment of the ILFD locking range. The proposed PLL is demonstrated using 90 nm CMOS. The calibration process converges within 100 mu sec at all 4-channels defined by the Wireless Gigabit Alliance (WiGig).
引用
收藏
页码：646 / 648
页数：3
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