Decomposing the proof of correctness of pipelined microprocessors

被引:0
|
作者
Hosabettu, R [1 ]
Srivas, M
Gopalakrishnan, G
机构
[1] Univ Utah, Dept Comp Sci, Salt Lake City, UT 84112 USA
[2] SRI Int, Comp Sci Lab, Menlo Park, CA 94025 USA
来源
COMPUTER AIDED VERIFICATION | 1998年 / 1427卷
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present a systematic approach to decompose and incrementally build the proof of correctness of pipelined microprocessors. The central idea is to construct the abstraction function using completion functions, one per unfinished instruction, each of which specifies the effect (on the observables) of completing the instruction. In addition to avoiding term-size and case explosion problem that limits the pure pushing approach, our method helps localize errors, and also handles stages with iterative loops. The technique is illustrated on a pipelined and a superscalar pipelined implementations of a subset of the DLX architecture. It has also been applied to a processor with out-of-order execution.
引用
收藏
页码:122 / 134
页数:13
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