High speed Viterbi decoding design for wireless LAN systems

被引：0

作者：

Gan, XD ^{[1
]}

Wang, ZJ ^{[1
]}

Zhang, HB ^{[1
]}

机构：

[1] VLSI Circuit Design & Test Dept, Inst Microelect, Singapore 117585, Singapore

来源：

APOC 2002: ASIA-PACIFIC OPTICAL AND WIRELESS COMMUNICATIONS; WIRELESS AND MOBILE COMMUNICATIONS II | 2002年 / 4911卷

关键词：

viterbi decoder; soft decision; WLAN; OFDM; ACS; trace-back;

D O I：

10.1117/12.480523

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the hardware design of a high speed Viterbi decoder for the IEEE 802.11a Wireless Local Area Networks (WLAN) application. A fully parallel Add-Compare-Select (ACS) and trace-back architecture is presented to achieve the decoding rate up to 54Mbps. Modulation scheme and coding rate dependent quntaization accuracy for soft decision Viterbi decoding is explored and a hardware implementation scheme with run-time configurable bit-length for soft decision is then proposed to reduce the system power consumption.

引用

页码：317 / 322

页数：6

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