Energy-Efficient and Calibration-Aware Fourier-Domain OCT Imaging Processor

被引:7
|
作者
Tang, Song-Nien [1 ]
Jan, Fu-Chiang [2 ]
机构
[1] Chung Yuan Christian Univ, Dept Informat & Comp Engn, Zhongli 32023, Taiwan
[2] Ind Technol Res Inst, Biomed Technol & Device Res Lab, Hsinchu 31040, Taiwan
关键词
Calibration; fast Fourier transform (FFT); optical coherence tomography (OCT); OPTICAL COHERENCE TOMOGRAPHY; HIGH-SPEED; FFT PROCESSOR; CORDIC ALGORITHM; IN-VIVO; PERFORMANCE; POLARIZATION; ARCHITECTURE; RESOLUTION; DISPLAY;
D O I
10.1109/TVLSI.2019.2894751
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a novel Fourier-domain optical coherence tomography (FDOCT) imaging processor capable of performing all image formation operations, including dc removal, resampling, real-valued fast Fourier transform (RFFT), and display rendering. Optimizing an RFFT unit through complexvalued FFT computation makes it possible to reduce the clock rate required for the RFFT and post-RFFT units by half, thereby enhancing energy efficiency. A novel resource-sharing scheme further enables calibration (i.e., calculation of resampling indices) awareness checking with minimal area overhead. This makes the proposed FDOCT imaging processor ideally suited to portable OCT application. A test chip operating at dual 80/ 40 MHz was designed using the Taiwan Semiconductor Manufacturing Company 0.18-mu m technology. In postlayout simulation of FDOCT imaging mode, the test chip was shown to consume only 283.6 mW, which represents a power saving of 29% compared to an equivalent design without optimization. The proposed design was also verified at the system level using a field programmable gate arrays (FPGA) platform. In evaluation experiments, we could achieve 78-KHz A-line scan and 30-fps 512 x 1000 OCT image display. The developed FPGA design also supports calibration awareness check using modest hardware resources.
引用
收藏
页码:1390 / 1403
页数:14
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