A Wet Process To Etch Arrayed Vias For Through Silicon Via Application Of 3D Packaging

In three-dimensional packaging (3D packaging) industry, through silicon via (TSV) technology is significant which acts as connection between chips and wafers. TSV technology achieves the interconnection through vertical vias and the formation of silicon vias mainly utilizes laser processing technique or deep reactive ion etching (DRIE) technique at the present stage. In this paper, an electrochemical etching to fabricate silicon vias is developed based on porous silicon. The focus of this study is to investigate the influence of etching current density, etching time, pore diameter of photoresist on the morphology of porous silicon. In fact, the morphology of porous silicon represents the morphology of the silicon via under ideal conditions. The thickness of porous silicon can reach to 50 micrometers when etching time is up to one hour, HF: C2H5OH = 1: 1, and current density is 20 mA/cm(2). However, there is lateral corrosion in the process of fabricating porous silicon. This study also analyzes the influence factor of lateral etching. When the amount of charge injected in the system is equivalent, the situation of lateral etching is alleviated with the small current density.