Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications

被引:10
|
作者
Manikandan, S. [1 ]
Balamurugan, N. B. [1 ]
Nirmal, D. [1 ]
机构
[1] Thiagarajar Coll Engn, Dept ECE, Madurai, Tamil Nadu, India
关键词
Analytical model; Junctionless; Double gate; Gate stack; Threshold voltage; Short channel effects; THRESHOLD VOLTAGE MODEL; HIGH-K DIELECTRICS; PERFORMANCE; MOSFET; DRAIN; DESIGN; ANALOG;
D O I
10.1007/s12633-019-00280-9
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
This paper proposes a 2-D analytical model developed for Double Gate Junctionless Transistor with a SiO2/HfO(2)stacked oxide structure. The model is solved by Poisson's equation using the variable separation method. The proposed model gives analytical expressions for electrostatic potential distribution, threshold voltage and drain current with the effects of depletion regions at source/drain side. Furthermore, the potential and drain current models are used to evaluate the Short Channel Effects (SCEs) of the proposed device. The electrical characteristics and SCEs are analyzed by different possible definitions of channel length, silicon thickness, equivalent oxide thickness, and depletion length variations. The developed model results are validated through comparison with Sentarus TCAD simulator results. In addition, the proposed device is also studied for the digital circuit performance of CMOS inverter circuit by the voltage transfer characteristics, transient analysis, and AC small signal analysis.
引用
收藏
页码:2053 / 2063
页数:11
相关论文
共 50 条
  • [41] Performance analysis of junctionless double gate VeSFET considering the effects of thermal variation - An explicit 2D analytical model
    Chaudhary, Tarun
    Khanna, Gargi
    SUPERLATTICES AND MICROSTRUCTURES, 2017, 103 : 102 - 112
  • [42] A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor
    Baruah, Ratul Kumar
    Paily, Roy P.
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2016, 15 (01) : 45 - 52
  • [43] A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor
    Ratul Kumar Baruah
    Roy P. Paily
    Journal of Computational Electronics, 2016, 15 : 45 - 52
  • [44] Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications
    Baidya, Achinta
    Lenka, Trupti Ranjan
    Baishya, Srimanta
    SUPERLATTICES AND MICROSTRUCTURES, 2016, 100 : 14 - 23
  • [45] Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2Cylindrical Gate TFETs
    Singh, Prince Kumar
    Baral, Kamalaksha
    Kumar, Sanjay
    Tripathy, Manas Ranjan
    Singh, Ashish Kumar
    Upadhyay, Rishibrind Kumar
    Chander, Sweta
    Jit, Satyabrata
    SILICON, 2021, 13 (06) : 1731 - 1739
  • [46] Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2 Cylindrical Gate TFETs
    Prince Kumar Singh
    Kamalaksha Baral
    Sanjay Kumar
    Manas Ranjan Tripathy
    Ashish Kumar Singh
    Rishibrind Kumar Upadhyay
    Sweta Chander
    Satyabrata Jit
    Silicon, 2021, 13 : 1731 - 1739
  • [47] Analytical model of drain current for ultra-thin body and double-gate schottky source/drain MOSFETs accounting for quantum effects
    Luan, Suzhen
    Liu, Hongxia
    Jia, Renxu
    Cai, Naiqiong
    Wang, Jin
    Kuang, Qianwei
    Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2008, 29 (05): : 869 - 874
  • [48] A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling
    Pandey, Pratyush
    Vishnoi, Rajat
    Kumar, M. Jagadesh
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2015, 14 (01) : 280 - 287
  • [49] A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling
    Pratyush Pandey
    Rajat Vishnoi
    M. Jagadesh Kumar
    Journal of Computational Electronics, 2015, 14 : 280 - 287
  • [50] Analytical Model to Study Temperature Dependent Negative Capacitance Effect on Long Channel Double Gate Ferroelectric Junctionless Transistor
    Mehta, Hema
    Kaur, Harsupreet
    2016 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC2016), 2016,