Computer security analysis through decompilation and high-level debugging

被引:6
|
作者
Cifuentes, C [1 ]
Waddington, T [1 ]
Van Emmerik, M [1 ]
机构
[1] Sun Microsyst Labs, Palo Alto, CA 94303 USA
关键词
D O I
10.1109/WCRE.2001.957846
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The extensive use of computers and networks worldwide has raised the awareness of the need for tools and techniques to aid in computer security analysis of binary code, such as the understanding of viruses, trojans, worms, back-doors and general security flaws, in order to provide immediate solutions with or without the aid of software vendors. This paper is a proposal for a high-level debugging tool to be used by computer security experts, which will reduce the amount of time needed in order to solve security-related problems in executable programs. The current state of the art involves the tracing of thousands of lines of assembly code using a standard debugger. A high-level debugger would be capable of displaying a high-level representation of an executable program in the C language, hence reducing the number of lines that need to be inspected by an order of magnitude (i.e. hundreds instead of thousands of lines). Effectively, these techniques will help in reducing the amount of time needed to trace a security flaw in an executable program, as well as reducing the costs of acquiring or training skilled assembler engineers.
引用
收藏
页码:375 / 380
页数:6
相关论文
共 50 条
  • [31] SECURITY IN HIGH-LEVEL NETWORK PROTOCOLS
    VOYDOCK, VL
    KENT, ST
    IEEE COMMUNICATIONS MAGAZINE, 1985, 23 (07) : 12 - 24
  • [32] High-level Debugging And Verification For FPGA-Based Multicore Architectures
    Abella, Oriol Arcas
    Cristal, Adrian
    Unsal, Osman S.
    2015 IEEE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM), 2015, : 135 - 142
  • [33] HIGH-LEVEL VLSI DESIGN SPECIFICATION VALIDATION USING ALGORITHMIC DEBUGGING
    NAGANUMA, J
    OGURA, T
    HOSHINO, T
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1994, E77A (12) : 1988 - 1998
  • [34] GENERALIZED PATH EXPRESSIONS - A HIGH-LEVEL DEBUGGING MECHANISM - PRELIMINARY DRAFT
    BRUEGGE, B
    HIBBARD, P
    SIGPLAN NOTICES, 1983, 18 (08): : 34 - 44
  • [35] High-level CHILL debugging system in cross-development environments
    Byun, Y
    Chung, YS
    Lee, BS
    PROCEEDINGS OF THE SIXTH EUROMICRO WORKSHOP ON PARALLEL AND DISTRIBUTED PROCESSING - PDP '98, 1998, : 211 - 216
  • [36] Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications
    Finder, Alexander
    Witte, Jan-Philipp
    Fey, Goerschwin
    PROCEEDINGS OF THE 2013 IEEE 16TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2013, : 60 - 65
  • [37] SECURITY MECHANISMS IN HIGH-LEVEL NETWORK PROTOCOLS
    VOYDOCK, VL
    KENT, ST
    COMPUTING SURVEYS, 1983, 15 (02) : 135 - 171
  • [38] HIGH-LEVEL SECURITY ARCHITECTURES AND THE KERBEROS SYSTEM
    RUSSELL, D
    COMPUTER NETWORKS AND ISDN SYSTEMS, 1990, 19 (3-5): : 201 - 214
  • [39] High-Level Approaches to Hardware Security: A Tutorial
    Pearce, Hammond
    Karri, Ramesh
    Tan, Benjamin
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2023, 22 (03)
  • [40] Enforcing high-level security properties for applets
    Pavlova, M
    Barthe, G
    Burdy, L
    Huisman, M
    Lanet, JL
    SMART CARD RESEARCH AND ADVANCED APPLICATIONS VI, 2004, 153 : 1 - 16