共 50 条
- [31] Maximizing common process latitude by integrated process development for 130 nm lithography OPTICAL MICROLITHOGRAPHY XV, PTS 1 AND 2, 2002, 4691 : 774 - 784
- [32] Effects of reticle birefringence on 193nm lithography OPTICAL MICROLITHOGRAPHY XX, PTS 1-3, 2007, 6520
- [33] A Wideband LNA for Wireless Multistandard GSM/WiMAX Receiver in 130nm CMOS Process 26TH IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE 2018), 2018, : 114 - 119
- [34] Leakage Current Compensation in Large Number of Inactive Synapses in a 130nm CMOS Process 2020 IEEE 63RD INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2020, : 460 - 463
- [35] 130nm Low Power Asynchronous AES Core 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017, : 2174 - 2177
- [36] Aberration tolerance for 130 nm lithography from viewpoint of process latitude JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1999, 38 (12B): : 7017 - 7021
- [37] Aberration tolerance for 130 nm lithography from viewpoint of process latitude Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 1999, 38 (12 B): : 7017 - 7021
- [38] Design and Implementation of High Speed Memory in 130nm INTERNATIONAL CONFERENCE ON METHODS AND MODELS IN SCIENCE AND TECHNOLOGY (ICM2ST-10), 2010, 1324 : 369 - +
- [39] Double dipole lithography for 65nm node and beyond: Defect sensitivity characterization and reticle inspection 24TH ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PT 1 AND 2, 2004, 5567 : 711 - 722