A Soft Error Robust 32kb SRAM Macro Featuring Access Transistor-Less 8T Cell in 65-nm

被引：0

作者：

Shah, Jaspal Singh ^{[1
]}

Nairn, David ^{[1
]}

Sachdev, Manoj ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, 200 Univ Ave West, Waterloo, ON N2L 3G1, Canada

来源：

2012 IEEE/IFIP 20TH INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP (VLSI-SOC) | 2012年

关键词：

UPSET;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An eight transistor static random access memory cell with an access transistor-less architecture is presented that shows high soft error robustness and low leakage current. A 32kb memory array is designed in 65 nm CMOS process. The cell provides 5.6x better immunity to soft errors when compared to a conventional SRAM cell. The cell shows 9.4x smaller read current than a 6T SRAM cell. The featured cell also shows read and write margin improvements.

引用

页码：275 / 278

页数：4