Design and Implementation of a Power and Speed Efficient Carry Select Adder on FPGA

被引：0
|
作者：
Chawla, Simarpreet Singh [1 ]
Aggarwal, Swapnil [1 ]
Goel, Nidhi [1 ]
Bhatia, Mantek Singh [2 ]
机构：
[1] Delhi Technol Univ, Dept Elect & Commun Engn, Delhi, India
[2] Amity Univ, Dept Comp Sci & Technol, Noida, India
来源：
PROCEEDINGS OF THE 10TH INDIACOM - 2016 3RD INTERNATIONAL CONFERENCE ON COMPUTING FOR SUSTAINABLE GLOBAL DEVELOPMENT | 2016年
关键词：
Carry Look Ahead Adder (CLAA); Carry Select Adder (CSA); Arithmetic and Logic Unit (ALU); Multiplexer (MUX);
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Adders are one of the most common unit in digital systems. The speed, power and area occupied by an adder play a vital role in Digital Signal Processing system, Image Processing system, etc. Hence, they play an important role in deciding the time period of the clock, the place and route of various units comprising of the system and total power consumed by the system. In this paper, we propose a new architecture for a modified sequential high speed carry select adder. We have given emphasis on optimizing the time period of the clock and power consumed, by using the carry ahead generation technique of Carry Look Ahead Adder (CLAA) and multiplexing technique of Carry Select Adder (CSA). The proposed CSA was implemented on Virtex-7 and results were calculated using Vivado Design Suite 2014.4.
引用
收藏
页码：571 / 576
页数：6
相关论文
共 50 条
  • [31] Design of Low Power and High Speed Modified Carry Select Adder for 16 bit Vedic Multiplier
    Prasad, Bhavani Y.
    Chokkakula, Ganesh
    Reddy, Srikanth P.
    Samhitha, N. R.
    2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
  • [32] A Comparative study on Low-Power and High Speed Carry Select Adder
    Reddy, G. Karthik
    Rao, D. Sharat Babu
    PROCEEDINGS OF 2015 IEEE 9TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO), 2015,
  • [33] Area and Power Efficient Carry Select Adder using 8T Full Adder
    Sathyabhama, B.
    Deepika, M.
    Deepthi, S.
    2015 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2015, : 969 - 973
  • [34] High-speed and energy efficient carry select adder (CSLA) dominated by carry generation logic
    Nam, Minho
    Choi, Yeonhun
    Cho, Kyoungrok
    MICROELECTRONICS JOURNAL, 2018, 79 : 70 - 78
  • [35] Design of Low Power and High Speed Ripple Carry Adder
    Archana, S.
    Durga, G.
    2014 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2014,
  • [36] An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic
    Manju, S.
    Sornagopal, V.
    2013 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN VLSI, EMBEDDED SYSTEM, NANO ELECTRONICS AND TELECOMMUNICATION SYSTEM (ICEVENT 2013), 2013,
  • [37] Low Power VLSI Design for Power and Area Effective Utilisation of Carry Select Adder
    Manjunatha, G. C.
    Singh, R. P.
    2017 INTERNATIONAL CONFERENCE ON CURRENT TRENDS IN COMPUTER, ELECTRICAL, ELECTRONICS AND COMMUNICATION (CTCEEC), 2017, : 606 - 610
  • [38] Design of Area and Delay Efficient Vedic Multiplier Using Carry Select Adder
    Gokhale, G. R.
    Gokhale, S. R.
    2015 IEEE INTERNATIONAL CONFERENCE ON INFORMATION PROCESSING (ICIP), 2015, : 295 - 300
  • [39] Design of High Speed Carry Save Adder using Carry Lookahead Adder
    Javali, Ravikumar A.
    Nayak, Ramanath J.
    Mhetar, Ashish M.
    Lakkannavar, Manjunath C.
    2014 INTERNATIONAL CONFERENCE ON CIRCUITS, COMMUNICATION, CONTROL AND COMPUTING (I4C), 2014, : 33 - 36
  • [40] Low Power High Performance Carry Select Adder
    Natarajan, P. B.
    Ghosh, Samit Kumar
    Karthik, R.
    2017 INTERNATIONAL CONFERENCE OF ELECTRONICS, COMMUNICATION AND AEROSPACE TECHNOLOGY (ICECA), VOL 2, 2017, : 601 - 603
12345