Performance Evaluation and Improvement of Chipset Assembly & Test Production Line Based on Variability

被引:0
|
作者
Li, Chang-Jun [1 ]
Xie, Zong-Shi [1 ]
Peng, Xin-Ran [1 ]
Li, Bo [1 ]
机构
[1] Univ Elect Sci & Technol China, Sch Aeronaut & Astronaut, Chengdu 611731, Sichuan, Peoples R China
基金
中国国家自然科学基金;
关键词
Performance evaluation and improvement; chipset assembly & test production line (CATPL); parameters; Littles law; variability; MANUFACTURING SYSTEMS; OPTIMIZATION; TIMES; QUEUE;
D O I
10.1007/s11633-018-1129-8
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Factory physics principles provided a method to evaluate the performance of a simple production line, whose fundamental parameters are known or given. However, it is difficult to obtain the exact and reasonable parameters in actual manufacturing environment, especially for the complex chipset assembly & test production line (CATPL). Besides, research in this field tends to focus on evaluation and improvement of CATPL without considering performance interval and status with variability level. A developed internal benchmark method is proposed, which established three-parameter method based on the Littles law. It integrates the variability factors, such as processing time, random failure time, and random repair time, to meet performance evaluation and improvement. A case study in a chipset assembly and test factory for the performance of CATPL is implemented. The results demonstrate the potential of the proposed method to meet performance evaluation and emphasise its relevance for practical applications.
引用
收藏
页码:186 / 198
页数:13
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